1. Field of the Invention
The present invention relates in general to a process for fabricating semiconductor read-only memory devices, and particularly relates to a process of simultaneous memory-content coding and identification code marking in the fabrication of read-only memory devices.
2. Technical Background
Read-only memory devices, herein referred to as ROM devices, are widely utilized in various kinds of digital electronic equipment that require the use of stored data and program codes. ROM semiconductor devices, specifically ROM IC's, are fabricated in processes that can be generally divided into two stages. Due to the different application purposes that are involved in the use of these ROM IC's, they can be fabricated with basically the same process steps up to the stage prior to memory cell content programing. The remaining fabrication process steps, after a particular memory content is designated for a ROM product, however, will be different, if the code mask that is utilized for the programing of the specific code content is considered. Basically, the code masks possess the particular mask patterns that correspond to the code contents of the manufactured ROMIC device. Any two code masks for the same type of ROM device with different code contents will have different mask patterns.
However, even after the code mask is utilized in the impurity implantation procedure that implants impurities into the memory cells of the programmed ROM device for the selective programing of the memory bits, and before the semiconductor wafer is processed as separate dies for the IC and packaged, ID code marking applied to the periphery of the wafer thereof must be utilized for the human identification of the ROM device. This is because all ROM IC devices contained on a wafer at this stage will appear the same to human eyes. The identification code marking made on the periphery area of the wafers that contain tens or hundreds of independent ROM dies may then be conveniently used for the identification of the different wafer products at this stage.
FIGS. 1a-1c respectively show the cross-sectional views of the memory cell unit of a conventional ROM device as depicted in selected steps of its process of fabrication. This depicted conventional ROM device is utilized herein for a brief description of the prior art. On the other hand, FIG. 2a schematically shows the top view of the memory cell unit of the conventional ROM device, and FIGS. 2b and 2c respectively show the cross-sectional views of the conventional ROM device as depicted by cutting along the two selected cross-sectioning lines II--II and II'--II' lines in FIG. 2a. The exemplified process as depicted in FIGS. 1a-1c and FIGS. 2a-2c include the programming of the code content, as well the implementation of the ID code marking. In the depicted drawings, the ROM device is fabricated on a P-type silicon substrate 1.
As is seen in the cross-sectional view of FIG. 1a, N-type impurities are implanted into the P-type substrate 1, forming a number of N-type bit lines 10 isolated from each other, as observed from the cross-sectional view. An ID code marking layer 100 is also formed along the periphery of the P-type silicon substrate 1. The formation of the code mark layer 100 may be, for example, the field oxide layer formed by the implementation of a local oxidation of silicon (LOCOS) procedure.
Then, regions other than the code mark layer 100 are further oxidized, forming the dielectric layer 12 with, for example, silicon oxides, that covers the surface of the P-type substrate 1 as well as the surface of the N-type bit lines 10. Since the bit lines 10 have N-type impurities implanted therein, therefore they sustain a faster rate of thermal oxidation, with the result that the dielectric layer 12 is formed more thickly over the surface of the bit lines 10 than at other areas of the surface of the substrate 1. This situation is schematically shown in the cross-sectional view of FIG. 1a.
Next, a number of word lines 14 are then formed, with the longitudinal direction thereof orthogonal to the longitudinal direction of the bit lines 10. As is well known in the art, the word lines 14 are parallel strips spaced-apart from each other. The word lines 14 may be formed by, for example, depositing a layer of polysilicon material with a thickness of about 3000.ANG., or, by subsequently depositing polysilicon and WSi.sub.x layers of about 1500.ANG., respectively.
Then, an oxide spacer 102 is formed at the end of the word lines 14. This may be formed by, for example, first depositing a layer of silicon oxide of about 2500.ANG., and then subjecting it to an etching-back process.
Referring next to FIG. 1b of the drawing. When the process proceeds to the programming of the memory cell content of the ROM device, a code mask 104 is formed by a lithography process with the required mask pattern. Then, with the shielding over the designated regions on the surface of the semiconductor substrate 1 as provided by the code mask 104, which shields the code mark layer 100, as well as those regions of the memory cell that not require memory bit programing, the desired regions over the surface of the substrate 1 are shielded for the implementation of an implantation procedure that implants P-type impurities, such as BF.sub.2 or B ions, into the memory cell regions to be programmed.
For example, when P-type impurities are implanted into the second type data regions 18 of the selected memory cells, while all other selected memory cells designated for the first type data regions 16 are shielded from implantation, as is shown schematically in FIG. 1b, the program/data code content of the ROM device will be suitably programmed. As is well known to persons skilled in the art, the implantation of P-type impurities into the second type data regions 18 allows the regions to have an increased threshold voltage. This means the memory cells with second type data regions 18 will be in an OFF state when accessed. All other memory cells with the first type data regions 16 will, in contrast, be in an ON state when accessed. Normally, the implanted P-type impurity may be, for example, boron or BF.sub.2, and the typical implantation energy level is about 130 keV, at an implantation dosage of about 2.times.10.sup.14 cm.sub.-2.
Then, as shown in FIG. 1c, the programming code mask layer 104 can be removed, and another lithography procedure may then be implemented, with the ID code mark masking layer 106 deployed over the surface of the substrate 1, so that the ID code mark 108 may be made in the ID code mark layer 100 in the designated peripheral area on the semiconductor wafer, that is, the silicon substrate 1.
With reference to FIG. 2a of the drawing, an ID code mark 108, which in this example made into the shape of a number "1", is formed for the purpose of human identification when the wafer is handled in the subsequent process stages. FIG. 2b, which schematically shows the cross section of the ROM device taken along the II--II line of FIG. 2a, clearly shows that the width of the second type data region 18 is wider than that of the bit lines 14. The reason for this is to allow for the alignment tolerance for the bit lines 14 in the fabrication procedure. This, however, signifies the need that the program/code and ID code mark be fabricated in two separate photomasking processes.
If, however, the intention is to make both the memory cell code programming and the ID code marking simultaneously in one lithography procedure for this conventional technique of ROM device fabrication, there is a risk of inadequately etching the exposed areas of the second type data regions 18 that are not covered by the bit lines 14. Refer to FIG. 2c, which shows the cross-sectional view of the cross section cut along the II'--II' line in FIG. 2a. In this cross section, the dielectric layer 12, which is exposed out of the coverage of the bit line 14, will also be subjected to the etching process that was intended primarily for the formation of the ID code mark 108 on the ID code marking layer 100. If the etching to the exposed dielectric layer 12 is excessive, inadequate conduction may result in these overly-etched regions of the memory cell, resulting in the erroneous data reading of the ROM device. The only method for avoiding this consequence in the prior art procedure of ROM device fabrication is to come out the coding of the memory cells and the making of the ID code mark in two separate photolithography procedures.